1. Field of the Invention
This invention relates to a drive circuit for a display apparatus, end more particularly to a drive circuit for a display apparatus which is capable of gray-scale display by an amplitude modulation drive. In this specification, a matrix type liquid crystal display apparatus will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatus such as electroluminescent (EL) display apparatus end plasma display apparatus.
2. Description of the Prior Art
When driving a liquid crystal display (LCD) apparatus, since the speed of response of a liquid crystal is very slow as compared with a luminescent material used in a cathode ray tube (CRT) display apparatus, a special drive circuit is used. That is, in a drive circuit for an LCD apparatus, video signals which are sequentially sent are not immediately supplied to respective pixels, but the video signals are sampled for each of the respective pixels in one horizontal period and held for the horizontal period. The held video signals are output at the same time at the beginning of the next horizontal period, or at an appropriate point of time in the next horizontal period. After the output of video signal voltages to the respective pixels are begun, the signal voltages are held for a period of time sufficiently over the speed of response of the liquid crystal.
In order to hold the signal voltages, a prior art drive circuit utilizes capacitors. FIG. 32 shows a Bighal voltage output circuit (a source driver) for supplying drive voltages to a plurality of pixels (in this case, 120 pixels) on one scanning line selected by e scanning signal. A portion for the nth pixel of the source driver is shown in FIG. 33. The portion includes an analog switch SW.sub.1, an sampling capacitor C.sub.SMP, an analog switch SW.sub.2, a holding capacitor C.sub.H, and an output buffer amplifier A. The operation of the signal voltage output in the prior art will be described with reference to the signal timing chart of FIG. 34. Analog video signals v.sub.s to be input to the analog switches SW.sub.1 are sequentially sampled in accordance with sampling clock signals T.sub.SMP -T.sub.SMP120 which correspond to the respective 120 pixels on one scanning line selected by each horizontal synchronizing signal H.sub.syn. By this sampling, the sequential instantaneous voltages V.sub.SMP1 -V.sub.SMP120 of the video signals v.sub.s are applied to the corresponding sampling capacitors C.sub.SMP. The nth sampling capacitor C.sub.SMP is charged up to the value of the video signal voltage V.sub.SMPn corresponding to the nth pixel, and holds this value. The signal voltages V.sub.SMP1 -V.sub.SMP120 which are sequentially sampled and held in one horizontal period are transferred from the sampling capacitors C.sub.SMP to the holding capacitors C.sub.H for holding outputs, in response to an output pulse OE which is supplied to all of the analog switches SW.sub.2 at the same time. Then the signal voltages V.sub.SMP1 -V.sub.SMP120 are output to source lines 0.sub.1 -0.sub.120 connected to the respective pixels through the buffer amplifiers A.
To the drive circuit described above, analog video signals are supplied. When video signals are supplied in the form of digital data, a drive circuit shown in FIG. 35 is used. For the sake of simplicity, the video signal data is composed of 2 bits (D.sub.0, D.sub.1). That is, video signal data have four values 0-3, and a signal voltage applied to each pixel is any one of four levels V.sub.0 -V.sub.3. FIG. 36 shows a portion for the nth source line 0.sub.n in the circuit. The portion of the circuit comprises a D-type flip-flop (sampling memory) M.sub.SMP at a first stage and a flip-flop (holding memory) M.sub.H at a second stage which are provided for the respective bits (D.sub.0, D.sub.1) of the video signal data, a decoder DEC, and analog switches ASW.sub.0 -ASW.sub.3 each of which is provided between corresponding one of four external voltage sources V.sub.0 -V.sub.3 and a source line o.sub.n.
The digital source driver operates as follows. The video signal data (D.sub.0, D.sub.1) are sampled at the rising of a sampling pulse T.sub.SMPn corresponding to the nth pixel, by the sampling memory M.sub.SMP. At the time when the sampling for one horizontal period is completed, an output pulse OE is fed to the holding memories M.sub.H. All the video signal data (D.sub.0, D.sub.1) held in the holding memories M.sub.H are simultaneously output to the respective decoders DEC. Each of the decoders DEC decodes the 2-bit video signal data (D.sub.0, D.sub.1). In accordance with the values (0 to 3), one of the analog switches ASW.sub.0 -ASW.sub.3 is conductive, and the corresponding one of the four external voltages V.sub.0 -V.sub.3 is output to the source line O.sub.n.
In the example shown in FIG. 36, since the video signal data is 2 bits, 4 (=2.sup.2) levels of external voltages (V.sub.0 -V.sub.3) to be supplied to the source line 0.sub.n are required. When a 4-bit video signal data is supplied, a signal voltage output circuit has a configuration shown in FIG. 37 in which 2.sup.4 =16 levels of external voltages (V.sub.0 -V.sub.3) are required. That is, in a drive circuit for a digital video signal constructed in such a manner, it is necessary to provide 2.sup.n levels of external voltages, for n-bit video signal data.
As described above, when the number of levels of the voltages to be externally supplied increases, the following problems (1) and (2) arise.
(1) With the increase in number of levels of voltages to be supplied, the size of a voltage supplying circuit is enlarged. Therefore, the production cost is increased.
(2) Since the number of input terminals of an LSI constituting the drive circuit including the above signal voltage output circuit increases. Such an is difficult to mount.